View ISL12032IVZ_4132532.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

(R)
ISL12032
Real Time Clock with 50/60 Hz clock and Crystal Backup
Data Sheet December 14, 2007 FN6618.0
Low Power RTC with Battery Backed SRAM and 50/60 Cycle AC Input and Xtal Back-up
The ISL12032 device is a low power real time clock with 50/60 AC input for timing synchronization. It also has an oscillator utilizing an external crystal for timing back-up, clock/calendar registers, intelligent battery back-up switching, battery voltage monitor, brownout indicator, integrated trickle charger for super capacitor, single periodic or polled alarms, POR supervisory function, and up to 4 Event Detect with time stamp. There are 128 bytes of battery-backed user SRAM. The oscillator uses a 50/60 cycle sine wave input, backed by an external, low-cost, 32.768kHz crystal. The real time clock tracks time with separate registers for hours, minutes, and seconds. The calendar registers contain the date, month, year, and day of the week. The calendar is accurate through year 2100, with automatic leap year correction and auto daylight savings correction.
Features
* 50/60 Cycle AC as a Primary Clock Input for RTC Timing * Redundant Crystal Clock Input Selectable by User - Dynamically Switch from AC Clock Input to Crystal in Case of Power Failure * Real Time Clock/Calendar - Tracks Time in Hours, Minutes, Seconds and tenths of a second - Day of the Week, Day, Month, and Year * Auto Daylight Saving Time Correction - Programmable Forward and Backward Dates * Security and Event Functions - Event Detection with Time Stamp - Stores First and Last Three Event Time Stamps * Separate FOUT Pin - 7 Selectable Frequency Outputs * Dual Alarms with Hardware and Register Indicators - Hardware Single Event or Pulse Interrupt Mode * Automatic Backup to Battery or Super Capacitor - VBAT Operation Down to 1.8V - 1.0A Battery Supply Current * Two Battery Status Monitors with Selectable Levels - Seven Selectable Voltages for Each Level - 1st Level, Trip Points from 4.675V to 2.125V - 2nd Level, Trip Points from 4.125V to 1.875V * VDD Power Brownout Monitor - Six Selectable Trip Levels, from 4.675V to 2.295V * Time Stamp during Power to Battery and Battery to Power Switchover * Integrated Trickle Charger - Four Selectable Charging Rates * 128 Bytes Battery-Backed User SRAM * I2C Interface - 400kHz Data Transfer Rate * Pb-free (RoHS compliant)
Pinout
ISL12032 (14 LD TSSOP) TOP VIEW
X1 X2 VBAT GND AC LV EVIN
1 2 3 4 5 6 7
14 13 12 11 10 9 8
VDD IRQ SCL SDA ACRDY FOUT EVDET
Applications
* Utility Meters * Control Applications * Security Related Applications * Vending Machines * White Goods * Consumer Electronics
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL12032 Ordering Information
PART NUMBER (Note) ISL12032IVZ* PART MARKING 12032 IVZ VDD RANGE 2.7V to 5.5V TEMP RANGE (C) -40 to +85 PACKAGE (Pb-free) 14 Ld TSSOP PKG DWG # M14.173
*Add "-T" suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Block Diagram
SDA SCL SDA BUFFER SCL BUFFER I2C INTERFACE SECONDS CONTROL LOGIC REGISTERS MINUTES HOURS DAY OF WEEK CRYSTAL OSCILLATOR POR/ LV COMPARE VTRIP SWITCH VBAT INTERNAL SUPPLY RTC DIVIDER FREQUENCY OUT DATE MONTH VDD YEAR ALARM CONTROL REGISTERS USER SRAM IRQ FOUT AC INPUT BUFFER AC POWER QUALITY EVALUATE LV ACRDY
X1 X2
AC
EVIN GND
EVDET
Functional Pin Descriptions
PIN NUMBER 1 2 3 4 5 6 7 8 9 SYMBOL X1 X2 VBAT GND AC LV EVIN EVDET FOUT DESCRIPTION The input of an inverting amplifier and is intended to be connected to one pin of an external 32.768kHz quartz crystal. X1 also can be driven directly from a 32.768kHz source with no crystal connected. The output of an inverting amplifier and is intended to be connected to one pin of an external 32.768kHz quartz crystal. X2 should be left open when X1 is driven from an external source. Battery voltage. This pin provides a backup supply voltage to the device. VBAT supplies power to the device in the event that the VDD supply fails. This pin should be tied to ground if not used. Ground. AC Input. The AC input pin accepts either 50Hz of 60Hz AC 2.5VP-P sine wave signal. Low Voltage detection output/Brownout Alarm. Open drain active low output. Event Input - The EVIN is a logic input pin that is used to detect an externally monitored event. When a high signal is present at the EVIN pin, an "event" is detected. Event Detect Output. Active when EVIN is triggered. Open Drain active low output. Frequency Output. Register selectable frequency clock output. CMOS output levels.
2
FN6618.0 December 14, 2007
ISL12032 Functional Pin Descriptions
PIN NUMBER 10 11 12 13 14 SYMBOL ACRDY SDA SCL IRQ VDD (Continued)
DESCRIPTION AC Ready. Open Drain output. When High, AC input signal is qualified for timing use. Serial Data. SDA is a bi-directional pin used to transfer serial data into and out of the device. It has an open drain output and may be wire OR'ed with other open drain or open collector outputs. Serial Clock. The SCL input is used to clock all serial data into and out of the device. Interrupt Output. Open Drain active low output. Interrupt output pin to indicate alarm is triggered. Power supply.
3
FN6618.0 December 14, 2007
ISL12032
Absolute Maximum Ratings
Voltage on VDD, VBAT, SCL, SDA, ACRDY, AC, LV, EVDET, EVIN, IRQ, FOUT pins (respect to ground) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V Voltage on X1 and X2 pins (respect to ground) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.5V ESD Rating Human Body Model (Per MIL-STD-883 Method 3014) . . . . .>2kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>200V
Thermal Information
Thermal Resistance (Typical, Note 1) JA (C/W) 14 Ld TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to +85C Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V Supply Voltage (VBAT) . . . . . . . . . . . . . . . . . . . . . . . . . 1.8V to 5.5V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTE: 1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
DC Operating Characteristics
SYMBOL VDD VBAT IDD1
Specifications apply for: VDD = 2.7 to 5.5V, TA = -40C to +85C, unless otherwise stated. CONDITIONS MIN (Note 10) 2.7 1.8 VDD = 5V, SCL, SDA = VDD VDD = 3V, SCL, SDA = VDD 27 16 43 9.0 1.0 0.8 0.7 TYP (Note 4) MAX (Note 10) 5.5 5.5 60 45 75 18.0 1.8 1.2 1.0 100 1 1 VDD = 5.5V, VBAT = 1.8V -150 -150 2.0 2.2 30 50 VDD = 5.5V, VBAT = 3.0V, TRKR01 = 0, TRKR00 = 0 VDD = 5.5V, VBAT = 3.0V, TRKR01 = 0, TRKR00 = 1 VDD = 5.5V, VBAT = 3.0V, TRKR01 = 1, TRKR00 = 0 VDD = 5.5V, VBAT = 3.0V, TRKR01 = 1, TRKR00 = 1 1300 2200 3600 7800 VDD 50mV 50 +150 +150 2.4 A nA A A mV mV V mV mV V mV UNITS V V A A A A A 3 3 2, 5 2, 3 2, 8 2, 8 2, 8 NOTES
PARAMETER Main Power Supply Battery Supply Voltage Supply Current
IDD2 IDD3 IBAT
Supply Current (I2C communications VDD = 5V active) Supply Current for Timekeeping at AC Input Battery Supply Current VDD = 5.5V at TA=+25C, FOUT disabled VBAT = 5.5V at TA=+25C VBAT = 2.7V VBAT = 1.8V
IBATLKG ILI ILO VBATM VPBM VTRIP VTRIPHYS VBATHYS RTRK
Battery Input Leakage Input Leakage Current on SCL I/O Leakage Current on SDA Battery Level Monitor Threshold Brownout Level Monitor Threshold VBAT Mode Threshold VTRIP Hysteresis VBAT Hysteresis Trickle Charge Resistance
VDD = 5.5V, VBAT = 1.8V TRKEN = 0
VTRKTERM VTRKHYS
VBAT Charging Termination Point Trickle Charge ON-OFF Hysteresis
4
FN6618.0 December 14, 2007
ISL12032
DC Operating Characteristics
SYMBOL Specifications apply for: VDD = 2.7 to 5.5V, TA = -40C to +85C, unless otherwise stated. (Continued) CONDITIONS MIN (Note 10) TYP (Note 4) MAX (Note 10) UNITS NOTES
PARAMETER
IRQ/ACRDY/LV/EVDET (OPEN DRAIN OUTPUTS) VOL Output Low Voltage VDD = 5V, IOL = 3mA VDD = 2.7V, IOL = 1mA FOUT (CMOS OUTPUT) VOL VOH EVIN IEVPU EVIN Pull-up Current VDD = 5.5V, VBAT = 3.0V VDD = 0V, VBAT = 1.8V VIL VIH IEVPD Input Low Voltage Input High Voltage EVIN Disabled Pull-down Current VDD = 5.5V 0.7 x VDD 200 1.0 100 3.0 8.0 600 0.3 x VDD A nA V V nA Output Low Voltage Output High Voltage IOH = 1mA 0.7 x VDD 0.3 x VDD V V 0.4 0.4 V V
Power-Down Timing Specifications apply for: VDD = 2.7 to 5.5V, TA = -40C to +85C, unless otherwise stated.
SYMBOL VDD SRPARAMETER VDD Negative Slew Rate CONDITIONS MIN TYP MAX (Note 10) (Note 4) (Note 10) 10 UNITS V/ms NOTES 6
I2C Interface Specifications Specifications apply for: VDD = 2.7 to 5.5V, TA = -40C to +85C, unless otherwise stated.
MIN (Note 10) -0.3 0.7 x VDD 0.05 x VDD VDD = 5V, IOL = 3mA TA = +25C, f = 1MHz, VDD = 5V, VIN = 0V, VOUT = 0V Any pulse narrower than the max spec is suppressed. SCL falling edge crossing 30% of VDD, until SDA exits the 30% to 70% of VDD window. 1300 10 0.4 TYP (Note 4) MAX (Note 10) UNITS 0.3 x VDD VDD + 0.3 V V V V pF
SYMBOL VIL VIH Hysteresis VOL CPIN
PARAMETER SDA and SCL Input Buffer LOW Voltage SDA and SCL Input Buffer HIGH Voltage SDA and SCL Input Buffer Hysteresis SDA Output Buffer LOW Voltage, Sinking 3mA SDA and SCL Pin Capacitance
TEST CONDITIONS
NOTES
fSCL tIN tAA
SCL Frequency Pulse Width Suppression Time at SDA and SCL Inputs SCL Falling Edge to SDA Output Data Valid
400 50 900
kHz ns ns
tBUF
Time the Bus Must be Free Before SDA crossing 70% of VDD the Start of a New Transmission during a STOP condition, to SDA crossing 70% of VDD during the following START condition. Clock LOW Time Clock HIGH Time Measured at the 30% of VDD crossing. Measured at the 70% of VDD crossing.
ns
tLOW tHIGH
1300 600
ns ns
5
FN6618.0 December 14, 2007
ISL12032
I2C Interface Specifications Specifications apply for: VDD = 2.7 to 5.5V, TA = -40C to +85C, unless otherwise stated.
(Continued) SYMBOL tSU:STA PARAMETER START Condition Setup Time TEST CONDITIONS SCL rising edge to SDA falling edge. Both crossing 70% of VDD. From SDA falling edge crossing 30% of VDD to SCL falling edge crossing 70% of VDD. From SDA exiting the 30% to 70% of VDD window, to SCL rising edge crossing 30% of VDD. From SCL falling edge crossing 30% of VDD to SDA entering the 30% to 70% of VDD window. From SCL rising edge crossing 70% of VDD, to SDA rising edge crossing 30% of VDD. From SDA rising edge to SCL falling edge. Both crossing 70% of VDD. From SCL falling edge crossing 30% of VDD, until SDA enters the 30% to 70% of VDD window. From 30% to 70% of VDD. From 70% to 30% of VDD. Total on-chip and off-chip MIN (Note 10) 600 TYP (Note 4) MAX (Note 10) UNITS ns NOTES
tHD:STA
START Condition Hold Time
600
ns
tSU:DAT
Input Data Setup Time
100
ns
tHD:DAT
Input Data Hold Time
0
900
ns
tSU:STO
STOP Condition Setup Time
600
ns
tHD:STO
STOP Condition Hold Time
600
ns
tDH
Output Data Hold Time
0
ns
tR tF Cb RPU
SDA and SCL Rise Time SDA and SCL Fall Time Capacitive loading of SDA or SCL
20 + 0.1 x Cb 20 + 0.1 x Cb 10 1
300 300 400
ns ns pF k
7, 9 7, 9 7, 9 7, 9
SDA and SCL Bus Pull-up Resistor Maximum is determined by Off-chip tR and tF. For Cb = 400pF, max is about 2k. For Cb = 40pF, max is about 15k
NOTES: 2. IRQ and FOUT Inactive. 3. VDD > VBAT +VBATHYS 4. Specified at TA =+25C. 5. FSCL = 400kHz. 6. In order to ensure proper timekeeping, the VDD SR- specification must be followed. 7. Parameter is not 100% tested. 8. VDD = 0V. IBAT increases at VDD voltages between 0.5V and 1.5V. 9. These are I2C specific parameters and are not tested, however, they are used to set conditions for testing devices to validate specification. 10. Parts are 100% tested at +25C. Over-temperature limits established by characterization and are not production tested.
6
FN6618.0 December 14, 2007
ISL12032 SDA vs SCL Timing
tF tHIGH tLOW tR
SCL tSU:STA tHD:STA SDA (INPUT TIMING)
tSU:DAT tHD:DAT tSU:STO
tAA SDA (OUTPUT TIMING)
tDH
tBUF
Symbol Table
WAVEFORM INPUTS Must be steady OUTPUTS Will be steady
May change from LOW to HIGH May change from HIGH to LOW Don't Care: Changes Allowed N/A
Will change from LOW to HIGH Will change from HIGH to LOW Changing: State Not Known Center Line is High Impedance
EQUIVALENT AC OUTPUT LOAD CIRCUIT FOR VDD = 5V 5.0V 1533 SDA AND IRQ/FOUT FOR VOL= 0.4V AND IOL = 3mA
100pF
FIGURE 1. STANDARD OUTPUT LOAD FOR TESTING THE DEVICE WITH VDD = 5.0V
7
FN6618.0 December 14, 2007
ISL12032 General Description
The ISL12032 device is a low power real time clock with 50/60 AC input for timing synchronization. It also has an oscillator utilizing an external crystal for timing back-up, clock/calendar registers, intelligent battery back-up switching, battery voltage monitor, brownout indicator, integrated trickle charger for super capacitor, single periodic or polled alarms, POR supervisory function, and up to 4 Event Detect with time stamp. There are 128 bytes of battery-backed user SRAM. The oscillator uses a 50/60 cycle sine wave input, backed by an external, low-cost, 32.768kHz crystal. The real time clock tracks time with separate registers for hours, minutes, and seconds. The calendar registers contain the date, month, year, and day of the week. The calendar is accurate through year 2100, with automatic leap year correction and auto daylight savings correction. The ISL12032's alarm can be set to any clock/calendar value for a match. Each alarm's status is available by checking the Status Register. The device also can be configured to provide a hardware interrupt via the IRQ pin. There is a repeat mode for the alarms allowing a periodic interrupt every minute, every hour, every day, etc. The device also offers a backup power input pin. This VBAT pin allows the device to be backed up by battery or Super Capacitor with automatic switchover from VDD to VBAT. The ISL12032 devices are specified for VDD = 2.7V to 5.5V and the clock/calendar portion of the device remains fully operational in battery backup mode down to 1.8V (Standby Mode). The VBAT level is monitored and warnings are reported against preselected levels. The first report is registered when the VBAT level falls below 85% of nominal level, the second level is set for 75% of nominal level. Battery levels are stored in the PWRBAT registers. The ISL12032 offers a "Brownout" alarm once the VDD falls below a pre-selected trip level. In the ISL12032, this allows the system microcontroller to save vital information to memory before complete power loss. There are six VDD trip levels for the brownout alarm. The event detection function accepts a normally low logic input, and when triggered will store the time/date information for the event. The first event is stored in the memory until reset; subsequent events are stored on-chip memory and the last 3 events are retained and accessible by performing an indexed register read.
Pin Descriptions
X1, X2
The X1 and X2 pins are the input and output, respectively, of an inverting amplifier. An external 32.768kHz quartz crystal is used with the device to supply a backup timebase for the real time clock if there is no AC input. The device also can be driven directly from a 32.768kHz source at pin X1, in which case, pin X2 should be left unconnected. No external load capacitors are needed for the X1 and X2 pins.
X1 X2
FIGURE 2. RECOMMENDED CRYSTAL CONNECTION
VBAT (Battery Input)
This input provides a backup supply voltage to the device. VBAT supplies power to the device in the event that the VDD supply fails. This pin can be connected to a battery, a Super Capacitor or tied to ground if not used.
AC (AC Input)
The AC input is the main clock input for the real time clock. It can be either 50Hz or 60Hz, sine wave. The preferred amplitude is 2.5VP-P, although amplitudes >0.25VDD are acceptable. An AC coupled (series capacitor) sine wave clock waveform is desired as the AC clock input provides DC biasing.
LV (Low Voltage)
This pin indicates the VDD supply is below the programmed level. This signal notifies a host processor that the main supply is low and requests action. It is an open drain active LOW output.
EVIN (Event Input)
The EVIN pin input detects an externally monitored event. When a HIGH signal is present at the EVIN pin, an "event" is detected.This input may be used for various monitoring functions, such as the opening of a detection switch on a chassis or door. The event detection circuit can be user enabled or disabled (see EVIN bit) and provides the option to be operational in battery backup modes (see EVATB bit). When the event detection is disabled, the EVIN pin is gated OFF. See "Functional Pin Descriptions" on page 2 for more details.
EVDET (Event Detect Output)
The EVDET is an open drain output, which will go low when an event is detected at the EVIN pin. If the event detection function is enabled, the EVDET output will go LOW and stay there until the EVT bit is cleared.
8
FN6618.0 December 14, 2007
ISL12032
IRQ (Interrupt Output)
This pin provides an interrupt signal output. This signal notifies a host processor that an alarm has occurred and requests action. It is an open drain active LOW output.
Battery Backup Mode (VBAT) to Normal Mode (VDD)
The ISL12032 device will switch from the VBAT to VDD mode when one of the following conditions occurs: Condition 1: VDD > VBAT + VBATHYS where VBATHYS 50mV Condition 2: VDD > VTRIP + VTRIPHYS where VTRIPHYS 30mV These power control situations are illustrated in Figures 3 and Figure 4.
FOUT (Frequency Output)
This pin outputs a clock signal, which is related to the crystal frequency. The frequency output is user selectable and enabled via the I2C bus. The options include seven different frequencies or disable. It is a CMOS output.
Serial Clock (SCL)
The SCL input is used to clock all serial data into and out of the device. The input buffer on this pin is always active (not gated). It is disabled when the backup power supply on the VBAT pin is activated to minimize power consumption.
Serial Data (SDA)
SDA is a bi-directional pin used to transfer data into and out of the device. It has an open drain output and may be OR'ed with other open drain or open collector outputs. The input buffer is always active (not gated) in normal mode. An open drain output requires the use of a pull-up resistor. The output circuitry controls the fall time of the output signal with the use of a slope controlled pull-down. The circuit is designed for 400kHz I2C interface speeds. It is disabled when the backup power supply on the VBAT pin is activated.
VDD VTRIP VBAT
BATTERY BACKUP MODE
2.2V 1.8V VBAT + VBATHYS
VBAT - VBATHYS
FIGURE 3. BATTERY SWITCHOVER WHEN VBAT < VTRIP
VDD, GND
Chip power supply and ground pins. The device will operate with a power supply from VDD = 2.7V to 5.5VDC. A 0.1F capacitor is recommended on the VDD pin to ground.
BATTERY BACKUP MODE
VDD VBAT VTRIP VTRIP
Functional Description
Power Control Operation
The power control circuit accepts a VDD and a VBAT input. Many types of batteries can be used with Intersil RTC products. For example, 3.0V or 3.6V Lithium batteries are appropriate, and battery sizes are available that can power the ISL12032 for up to 10 years. Another option is to use a Super Capacitor for applications where VDD is interrupted for up to a month. See the "Application Section" on page 24 for more information.
3.0V 2.2V
VTRIP + VTRIPHYS
FIGURE 4. BATTERY SWITCHOVER WHEN VBAT > VTRIP
Normal Mode (VDD) to Battery Backup Mode (VBAT)
To transition from the VDD to VBAT mode, both of the following conditions must be met: Condition 1: VDD < VBAT - VBATHYS where VBATHYS 50mV Condition 2: VDD < VTRIP where VTRIP 2.2V
The I2C bus is normally deactivated in battery backup mode to reduce power consumption, but can be enabled by setting the I2CBAT bit. All the other inputs and outputs of the ISL12032 are active during battery backup mode unless disabled via the control register.
Power Failure Detection
The ISL12032 provides a Real Time Clock Failure Bit (RTCF) to detect total power failure. It allows users to determine if the device has powered up after having lost all power to the device (both VDD and VBAT very near 0.0VDC). Note that in cases where the VBAT input is at 0.0V and the VDD input dips to <1.8V, then recovers to normal level, the SRAM registers may not retain their values (corrupted bits or bytes may result).
9
FN6618.0 December 14, 2007
ISL12032
Brownout Detection
The ISL12032 monitors the VDD level continuously and provides a warning if the VDD level drops below prescribed levels. There are six levels that can be selected for the trip level. These values are 85% below popular VDD levels. The LVDD bit in the SRDC register will be set to "1" when Brownout is detected. Note that the I2C serial bus remains active until the Battery VTRIP level is reached. bit is set, a single read of the SRDC status register will clear them. The pulsed interrupt mode (setting the IM bit to "1") activates a repetitive or recurring alarm. Hence, once the alarm is set, the device will continue to output a pulse for each occurring match of the alarm and present time. The Alarm pulse will occur as often as every minute (if only the nth second is set) or as infrequently as once a year (if at least the nth month is set). During pulsed interrupt mode, the IRQ pin will be pulled LOW for 250ms and the alarm status bit (ALM0 or ALM1) will be set to "1". The alarm function is not available during battery backup mode.
Battery Level Monitor
The ISL12032 has a built in warning feature once the VBAT battery level drops first to 85% and then to 75% of the battery's nominal VBAT level. When the battery voltage falls to between 85% and 75%, the LBAT85 bit is set in the SRDC register. When the level drops below 75%, both LBAT85 and LBAT75 bits are set in the SRDC register. The trip levels for the 85% and 75% levels are set using the PWRBAT register. The Battery Timestamp Function permits recovering the time/date when VDD power loss occurred. Once the VDD is low enough to enable switchover to the battery, the RTC time/date are written into the TSV2B section. If there are multiple power-down cycles before reading these registers, the first values stored in these registers will be retained and ensuing events will be ignored. These registers will hold the original power-down value until they are cleared by writing "00h" to each register or setting the CLRTS bit to "1". The VDD Timestamp Function permits recovering the time/date when VDD recovery occurred. Once the VDD is high enough to enable switchover to VDD, the RTC time/date are written into the TSB2V register. If there are multiple power-down cycles before reading these registers, the most recent event is retained in these registers and the previous events will be ignored. These registers will hold the original power-down value until they are cleared by writing "00h" to each register.
Frequency Output Mode
The ISL12032 has the option to provide a clock output signal using the FOUT CMOS output pin. The frequency output mode is set by using the FO bits to select 7 possible output frequency values from 1.0Hz to 32.768kHz, and disable. The frequency output can be enabled/disabled during battery backup mode by setting the FOBATB bit to "0". When the AC input is qualified (within the parameters of AC qualification) then the Frequency Output for values 50/60Hz and below are derived from the AC input clock. Higher frequency FOUT values are derived from the crystal. If the AC clock input is not qualified, then all FOUT values are derived from the crystal.
General Purpose User SRAM
The ISL12032 provides 128 bytes of user SRAM. The SRAM will continue to operate in battery backup mode. However, it should be noted that the I2C bus is disabled in battery backup mode unless enabled by the I2CBAT bit.
I2C Serial Interface
The ISL12032 has an I2C serial bus interface that provides access to the control and status registers and the user SRAM. The I2C serial interface is compatible with other industry I2C serial bus protocols using a bi-directional data signal (SDA) and a clock signal (SCL). The I2C bus normally operates down to the VDD trip point set in the PWRVDD register. It can also operate in battery backup mode by setting the I2CBAT bit to "1", in which case operation will be down to VBAT = 1.8V.
Real Time Clock Operation
The Real Time Clock (RTC) maintains an accurate internal representation of tenths of a second, second, minute, hour, day of week, date, month, and year. The RTC also has leapyear correction. The clock also corrects for months having fewer than 31 days and has a bit that controls 24 hour or AM/PM format. When the ISL12032 powers up after the loss of both VDD and VBAT, the clock will not begin incrementing until at least one byte is written to the clock register.
Register Descriptions Alarm Operation
The alarm mode is enabled via the MSB bit. Single event or interrupt alarm mode is selected via the IM bit. The standard alarm allows for alarms of time, date, day of the week, month, and year. When a time alarm occurs in single event mode, the IRQ pin will be pulled low and the corresponding alarm status bit (ALM0 or ALM1) will be set to "1". The status bits can be written with a "0" to clear, or if the ARST The battery-backed registers are accessible following an I2C slave byte of "1101 111x" and reads or writes to addresses [00h:47h]. The defined addresses and default values are described in the Table 1. The battery backed general purpose SRAM has a different slave address (1010 111x), so it is not possible to read/write that section of memory while accessing the registers.
10
FN6618.0 December 14, 2007
ISL12032
REGISTER ACCESS The contents of the registers can be modified by performing a byte or a page write operation directly to any register address. The registers are divided into 10 sections. They are: 1. Real Time Clock (8 bytes): Address 00h to 07h. 2. Status (2 bytes): Address 08h to 09h. 3. Counter (2 bytes): Address Ah to Bh. 4. Control (9 bytes): 0Ch to 14h. 5. Day Light Saving Time (8 bytes): 15h to 1Ch 6. Alarm 0/1 (12 bytes):1Dh to 28h 7. Time Stamp for Battery Status (5 bytes): Address 29h to 2Dh. 8. Time Stamp for VDD Status (5 bytes): Address 2Eh to 32h. 9. Time Stamp for Event Status (5 bytes):33h to 37h. Write capability is allowable into the RTC registers (00h to 07h) only when the WRTC bit (bit 6 of address 0Ch) is set to "1". A multi-byte read or write operation is limited to one section per operation. Access to another section requires a new operation. A read or write can begin at any address within the section. A register can be read by performing a random read at any address at any time. This returns the contents of that register location. Additional registers are read by performing a sequential read. For the RTC and Alarm registers, the read instruction latches all clock registers into a buffer, so an update of the clock does not change the time being read. At the end of a read, the master supplies a stop condition to end the operation and free the bus. After a read, the address remains at the previous address +1 so the user can execute a current address read and continue reading the next register. It is only necessary to set the WRTC bit prior to writing into the RTC registers. All other registers are completely accessible without setting the WRTC bit.
11
FN6618.0 December 14, 2007
ISL12032
TABLE 1. REGISTER MEMORY MAP (X indicates writes to these bits have no effect on the device) REG NAME SC MN HR DT RTC MO YR DW SS SRDC Status SRAC ACCNT Counter EVTCNT INT FO EVIC EVIX Control TRICK PWRVDD PWRBAT AC FTR DstMoFd DstDwFd DstDtFd DstHrFd DSTCR DstMoRv DstDwRv DstDtRv DstHrRv SCA0 MNA0 HRA0 Alarm0 DTA0 MOA0 DWA0 BIT 7 0 0 MIL 0 0 YR23 0 0 BMODE X AXC7 EVC7 ARST X X X X CLRTS X AC5060 X DSTE 0 0 HrFdMIL 0 0 0 HrRvMIL ESCA0 EMNA0 EHRA0 EDTA0 EMOA0 EDWA0 6 SC22 MN22 0 0 0 YR22 0 0 DSTADJ X AXC6 EVC6 WRTC X EVBATB X X X BHYS ACENB X 0 DwFdE 0 0 0 DwRvE 0 0 SCA022 MNA021 0 0 0 0 5 SC21 MN21 HR21 DT21 0 YR21 0 0 ALM1 X AXXC5 EVC5 IM X EVIM X X I2CBAT VB85Tp2 ACRP1 X 0 WkFd12 DtFd21 HrFd21 0 WkRv12 DtRv21 HrRv21 SCA021 MNA020 HRA021 DTA021 0 0 4 SC20 MN20 HR20 DT20 MO20 YR20 0 0 ALM0 XOSCF AXC4 EVC4 X FOBATB EVEN X X LVENB VB85Tp1 ACRP0 ACMIN MoFd20 WkFd11 DtFd20 HrFd20 MoRv20 WkRv11 DtRv20 HrRv20 SCA020 MNA013 HRA020 DTA020 MOA020 0 3 SC13 MN13 HR13 DT13 MO13 YR13 0 SS3 LVDD X AXC3 EVC3 X X EHYS1 X X X VB85Tp0 ACFP1 XDTR3 MoFd13 WkFd10 DtFd13 HrFd13 MoRv13 WkRv10 DtRv13 HrRv13 SCA013 MNA012 HRA013 DTA013 MOA013 0 2 SC12 MN12 HR12 DT12 MO12 YR12 DW2 SS2 LBAT85 X AXC2 EVC2 X FO2 EHYS0 0 TRKEN VDDTrip2 BV75Tp2 ACFP0 XDTR2 MoFd12 DwFd12 DtFd12 HrFd12 MoRv12 DwRv12 DtRv12 HrRv12 SCA012 MNA011 HRA012 DTA012 MOA012 DWA02 1 SC11 MN11 HR11 DT11 MO11 YR11 DW1 SS1 LBAT75 ACFAIL AXC1 EVC1 ALE1 FO1 ESMP1 EVIX1 TRKRO1 VDDTrip1 VB75Tp1 ACFC1 XDTR1 MoFd11 DwFd11 DtFd11 HrFd11 MoRv11 DwRv11 DtRv11 HrRv11 SCA011 MNA011 HRA011 DTA011 MOA011 DWA01 0 SC10 MN10 HR10 DT10 MO10 YR10 DW0 SS0 RTCF ACRDY AXC0 EVC0 ALE0 FO0 ESMP0 EVIX0 TRKRO0 VDDTrip0 VB75Tp0 ACFC0 XDTR0 MoFd10 DwFd10 DtFd10 HrFd10 MoRv10 DwRv10 DtRv10 HrRv10 SCA010 MNA010 HRA010 DTA010 MOA010 DWA00 RANGE 0 to 59 0 to 59 0 to 23 1 to 31 1 to 12 0 to 99 0 to 6 0 to 9 N/A N/A 0 to 127 0 to 127 N/A N/A N/A N/A N/A N/A N/A N/A N/A 1 to 12 0 to 6 1 to 31 0 to 23 1 to 12 0 to 6 1 to 31 0 to 23 0 to 59 0 to 59 0 to 23 1 to 31 1 to 12 0 to 6 DEFAULT 00h 00h 00h 01h 01h 00h 00h 00h 01h 00h 00h 00h 01h 00h 00h 00h 00h 00h 00h 00h 00h 04h 00h 01h 02h 10h 00h 01h 02h 00h 00h 00h 01h 01h 00h
ADDR SECTION 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h
12
FN6618.0 December 14, 2007
ISL12032
TABLE 1. REGISTER MEMORY MAP (X indicates writes to these bits have no effect on the device) REG NAME SCA1 MNA1 HRA1 Alarm1 DTA1 MOA1 DWA1 SCVB MNVB TSV2B HRVB DTVB MOVB SCBV MNBV TSB2V HRBV DTBV MOBV SCT MNT TSEVT HRT DTT MOT BIT 7 ESCA1 EMNA1 EHRA1 EDTA1 EMOA1 EDWA1 X X MILVB X X X X MILBV X X X X MILT X X 6 SCA122 MNA122 0 0 0 0 SCBV22 MNVB22 X X X SCBV22 MNBV22 X X X SCT22 MNT22 X X X 5 SCA121 MNA121 HRA121 DTA121 0 0 SCBV21 MNVB21 HRVB21 DTVB21 X SCBV21 MNBV21 HRBV21 DTBV21 X SCT21 MNT21 HRT21 DTT21 X 4 SCA120 MNA120 HRA120 DTA120 MOA120 0 SCBV20 MNVB20 HRVB20 DTVB20 MOVB20 SCBV20 MNBV20 HRBV20 DTBV20 MOBV20 SCT20 MNT20 HRT20 DTT20 MOT20 3 SCA113 MNA113 HRA113 DTA113 MOA113 0 SCVB13 MNVB13 HRVB13 DTVB13 MOVB13 SCBV13 MNBV13 HRBV13 DTBV13 MOBV13 SCT13 MNT13 HRT13 DTT13 MOT13 2 SCA112 MNA112 HRA112 DTA112 MOA112 DWA12 SCVB12 MNVB12 HRVB12 DTVB12 MOVB12 SCBV12 MNBV12 HRBV12 DTBV12 MOBV12 SCT12 MNT12 HRT12 DTT12 MOT12 1 SCA111 MNA111 HRA111 DTA111 MOA111 DWA11 SCVB11 MNVB11 HRVB11 DTVB11 MOVB11 SCBV11 MNBV11 HRBV11 DTBV11 MOBV11 SCT111 MNT11 HRT11 DTT11 MOT11 0 SCA110 MNA110 HRA110 DTA110 MOA110 DWA10 SCVB10 MNVB10 HRVB10 DTVB10 MOVB10 SCBV10 MNBV10 HRBV10 DTBV10 MOBV10 SCT10 MNT10 HRT10 DTT10 MOT10 RANGE 0 to 59 0 to 59 0 to 23 1 to 31 1 to12 0 to 6 0 to 59 0 to 59 0 to 23 1 to 31 1 to 12 0 to 59 0 to 59 0 to 23 1 to 31 1 to 12 0 to 59 0 to 59 0 to 23 1 to 31 1 to 12 DEFAULT 00h 00h 00h 01h 01h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h
ADDR SECTION 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h
Real Time Clock Registers
Addresses [00h to 07h]
RTC REGISTERS (SC, MN, HR, DT, MO, YR, DW, SS) These registers depict BCD representations of the time. As such, SC (Seconds) and MN (Minutes) range from 0 to 59, HR (Hour) can be either 12-hour or 24-hour mode, DT (Date) is 1 to 31, MO (Month) is 1 to 12, YR (Year) is 0 to 99, DW (Day of the Week) is 0 to 6, and SS (Sub-Second) is 0 to 9. The SubSecond register is read-only and will clear to "0" count each time there is a write to a register in the RTC section. The DW register provides a Day of the Week status and uses three bits DW2 to DW0 to represent the seven days of the week. The counter advances in the cycle 0-1-2-3-4-5-6-0-12.... The assignment of a numerical value to a specific day of the week is arbitrary and may be decided by the system software designer. The default value is defined as "0". 24 HOUR TIME If the MIL bit of the HR register is "1", the RTC uses a 24-hour format. If the MIL bit is "0", the RTC uses a 12-hour format and HR21 bit functions as an AM/PM indicator with a
"1" representing PM. The clock defaults to 12-hour format time with HR21 = "0". LEAP YEARS Leap years add the day February 29 and are defined as those years that are divisible by 4. Years divisible by 100 are not leap years, unless they are also divisible by 400. This means that the year 2000 is a leap year and the year 2100 is not. The ISL12032 does not correct for the leap year in the year 2100.
Status Registers (SR)
Addresses [08h to 09h]
The Status Registers consist of the DC and AC status registers (see Tables 2 and 3).
Status Register (SRDC)
The Status Register DC is located in the memory map at address 08h. This is a volatile register that provides status of RTC failure (RTCF), Battery Level Monitor (LBAT85, LBAT75), VDD level monitor (LVDD), Alarm0 or Alarm1 trigger, Daylight Saving Time adjustment, and Battery active mode.
13
FN6618.0 December 14, 2007
ISL12032
TABLE 2. STATUS REGISTER DC (SRDC) ADDR
08h
Status Register (SRAC)
1 0 ADDR
09h
7
6
5
4
3
2
TABLE 3. STATUS REGISTER AC (SRAC) 7
X
BMODE DSTADJ ALM1 ALM0 LVDD LBAT85 LBAT75 RTCF
6
X
5
X
4
XOSCF
3
X
2
X
1
ACFAIL
0
ACRDY
BATTERY ACTIVE MODE (BMODE) Indicates that the device is operating from the VBAT input. A "1" indicates Battery Mode and a "0" indicates power from VDD mode. The I2CBAT bit must be set to "1" and the device must be in VBAT mode in order for a valid "1" read from this bit. DAYLIGHT SAVING TIME ADJUSTMENT BIT (DSTADJ) DSTADJ is the Daylight Saving Time Adjustment Bit. It indicates that daylight saving time adjustment has happened. The bit will be set to "1" when the Forward DST event has occured. The bit will stay set until the Reverse DST event has happened. The bit will also reset to "0" when the DSTE bit is set to "0" (DST function disabled). The bit can be forced to "1" with a write to the Status Register. The default value for DSTADJ is "0". ALARM BITS (ALM0 AND ALM1) These bits announce if an alarm matches the real time clock. If there is a match, the respective bit is set to "1". This bit can be manually reset to "0" by the user or automatically reset by enabling the auto-reset bit (see ARST bit). A write to this bit in the SR can only set it to "0", not "1". An alarm bit that is set by an alarm occurring during an SR read operation will remain set after the read operation is complete. LOW VDD INDICATOR BIT (LVDD) Indicates VDD dropped below the pre-selected trip level. (Brownout Mode). The Trip points for Brownout levels are selected by three bits VDDTrip2, VDDTrip1 and VDDTrip0 in the PWRVDD registers. LOW BATTERY INDICATOR 85% BIT (LBAT85) Indicates battery level dropped below the pre-selected trip level (85% of battery voltage). The trip point is set by three bits: VB85Tp2, VB85Tp1 and VB85Tp0 in the PWRBAT register. LOW BATTERY INDICATOR 75% BIT (LBAT75) Indicates battery level dropped below the pre-selected trip level (75% of battery voltage). The trip point is set by three bits: VB75Tp2, VB75Tp1 and VB75Tp0 in the PWRBAT register. REAL TIME CLOCK FAIL BIT (RTCF) This bit is set to a "1" after a total power failure. This is a read only bit that is set by hardware (internally) when the device powers up after having lost all power (defined as VDD = 0V and VBAT = 0V). The bit is set regardless of whether VDD or VBAT is applied first. The loss of only one of the supplies does not set the RTCF bit to "1". The first valid write to the RTC section after a complete power failure resets the RTCF bit to "0" (writing one byte is sufficient).
The Status Register AC is located in the memory map at address 09h. This is a volatile register that provides status of Crystal Failure (XOSCF), AC Failed (ACFAIL) and AC Ready (ACRDY). CRYSTAL OSCILLATOR FAIL BIT (XOSCF) Indicates Crystal Oscillator has stopped if XOSCF = 1. When the crystal oscillator has resumed operation, the XOSCF bit is reset to "0". AC FAIL (ACFAIL) This bit announces the status of the AC input. If ACFAIL = 1, then the AC input frequency and amplitude qualification check has failed. ACFAIL is reset to "0" when the AC input meets the preset requirements (see "AC (AC Input)" on page 8). AC READY (ACRDY) This bit announces the status of the AC input. If ACRDY=1, then the AC input has passed the qualification parameter check (as set by ACFC and ACFP bits) for the time prescribed by ACRP and is used for the RTC clock. When ACRDY = 0 the AC input failed the qualification requirements and the crystal oscillator clock is used for the RTC clock (see "AC (AC Input)" on page 8). When ACFAIL transitions from "1" to "0" (from failed to pass), then the timer set by ACRP will determine the delay until ACRDY transitions from "0" to "1". ACRDY will be set to "0" immediately after ACRDY is set to "0" (failed AC input), indicating the crystal oscillator is the RTC clock.
Counter Registers
Addresses [0Ah to 0Bh]
These registers will count the number of times AC failure occurs and the number of times an event occurs. These registers are 8-bits each and will count up to 255.
AC COUNT (ACCNT)
TABLE 4. AC COUNTER REGISTER (ACCNT) ADDR
0Ah
7
AXC7
6
AXC6
5
AXC5
4
AXC4
3
AXC3
2
AXC2
1
AXC1
0
AXC0
The ACCNT register increments automatically each time the AC input switches to the crystal backup. The register is set to 00h on initial power-up. The maximum count is 255, and will stay at that value until set to zero via an I2C write.
14
FN6618.0 December 14, 2007
ISL12032
Event Count (EVTCNT)
TABLE 5. EVENT COUNTER REGISTER (EVTCNT) ADDR 0Bh 7 6 5 4 3 2 1 0
22h) or the Alarm1 section (23h to 28h). When the IM bit is cleared to "0", the alarm will operate in standard mode, where the IRQ pin will be set LOW until both the ALM0/ALM1 status bits are cleared to "0". ALARM 1 (ALE 1) This bit enables the Alarm1 function. When ALE1 = "1", a match of the RTC section with the Alarm1 section will result is setting the ALM1 status bit to "1" and the IRQ output LOW. When set to "0", the Alarm1 function is disabled. ALARM 0 (ALE 0) This bit enables the Alarm0 function. When ALE0 = 1, a match of the RTC section with the Alarm1 section will result is setting the ALM0 status bit to "1" and the IRQ output LOW. When set to "0", the Alarm0 function is disabled.
EVC7 EVC6 EVC5 EVC4 EVC3 EVC2 EVC1 EVC0
The EVTCNT register increments automatically each time an event occurs. The register is set to 00h on initial power-up. The maximum count is 255, and will stay at that value until set to zero via an I2C write. Performing a write of 00h to this register will clear the contents of this register and all levels of the TSEVT section. A clear to this register should be done with care. Write event index register zero only selects first event time stamp. Write event count EVNTCNT zero will both clear event counter and all time stamps.
Frequency Out Register (FO)
TABLE 7. FREQUENCY OUT REGISTER (FO) ADDR 0Dh 7 X 6 X 5 X 4 FOBATB 3 X 2 1 0
Control Registers
Addresses [0Ch to 14h]
The control registers (INT, FO, EVIC, EVIX, TRICK, PWRVDD, PWRBAT, AC, and FTR) contain all the bits necessary to control the parametric functions on the ISL12032.
FO2 FO1 FO0
FREQUENCY OUTPUT AND INTERRUPT BIT (FOBATB) This bit enables/disables FOUT during battery backup mode (i.e. VBAT power source active). When the FOBATB is set to "1" the FOUT pin is disabled during battery backup mode. When the FOBATB is cleared to "0", the FOUT pin is enabled during battery backup mode (default). Note that FOUT is a CMOS output and needs no pull-up resistor. Note also that battery current drain will be higher with FOUT enabled in battery backup mode. FREQUENCY OUT CONTROL BITS (FO <2:0>) These bits enable/disable the frequency output function and select the output frequency at the FOUT pin. See Table 8 for frequency selection. Note that frequencies from 4096Hz to 32768Hz are derived from the Crystal Oscillator, and the 1.0, 10, and 50/60Hz frequencies are derived from the AC clock input. The exception to this is when the AC input qualification has failed, and the crystal oscillator is used for the 1.0Hz FOUT.
TABLE 8. FREQUENCY SELECTION OF FOUT PIN FREQUENCY, FOUT 32768 16372 8192 4096 50/60 10 1 UNITS Hz Hz Hz Hz Hz Hz Hz FO2 0 0 0 0 1 1 1 FO1 0 0 1 1 0 0 1 FO0 0 1 0 1 0 1 0
Interrupt Control Register (INT)
TABLE 6. INTERRUPT CONTROL REGISTER (INT) ADDR 0Ch 7 ARST 6 WRTC 5 IM 4 X 3 X 2 X 1 0
ALE1 ALE0
AUTOMATIC RESET BIT (ARST) This bit enables/disables the automatic reset of the ALM0, ALM1, LVDD, LBAT85, and LBAT75 status bits only. When ARST bit is set to "1", these status bits are reset to "0" after a valid read of the SRDC Register (with a valid STOP condition). When the ARST is cleared to "0", the user must manually reset the ALM0, ALM1, LVDD, LBAT85, and LBAT75 bits. WRITE RTC ENABLE BIT (WRTC) The WRTC bit enables or disables write capability into the RTC Register section. The factory default setting of this bit is "0". Upon initialization or power-up, the WRTC must be set to "1" to enable the RTC. Upon the completion of a valid write (STOP), the RTC starts counting. The RTC internal 1Hz signal is synchronized to the STOP condition during a valid write cycle. This bit will remain set until reset to "0" or a complete power-down occurs (VDD = VBAT = 0.0V) ALARM INTERRUPT MODE BIT (IM) This bit enables/disables the interrupt mode of the alarm function. When the IM bit is set to "1", the alarms will operate in the interrupt mode, where an active low pulse width of 250ms will appear at the IRQ pin when the RTC is triggered by either alarm as defined by the Alarm0 section (1Dh to
15
FN6618.0 December 14, 2007
ISL12032
Event Detection Register (EVIC)
TABLE 9. EVENT DETECTION REGISTER (EVIC) ADDR
0Eh
.
TABLE 11. EVENT INPUT SAMPLING RATE ESMP1 ESMP2 0 1 0 1 SAMPLING RATE Always ON 2 Hz 1 Hz 1/4 Hz
7
X
6
5
4
3
2
1
0
0 0 1
EVBATB EVIM
EVEN EHYS1 EHYS0 ESMP1 ESMP0
EVENT OUTPUT IN BATTERY MODE ENABLE BIT (EVBATB) This bit enables/disables the EVDET pin during battery backup mode (i.e. VBAT pin supply ON). When the EVBATB is set to "1", the Event Detect Output is disabled in battery backup mode. When the EVBATB is cleared to "0", the Event Detect output is enabled in battery backup mode. This feature can be used to save power during battery mode. EVENT OUTPUT PULSE MODE (EVIM) This bit controls the EVDET pin output mode. With EVIM = 0, the output is in normal mode and when an event is triggered, the output will be set LOW until reset. With EVIM = 1, the output is in pulse mode and when an event is triggered, the device will generate a 200ms to 300ms pulse at the EVDET output. EVENT DETECT ENABLE (EVEN) This bit enables/disables the Event Detect function of the ISL12032. When this bit is set to "1", the Event Detect is active. When this bit is cleared to "0", the Event Detect is disabled. EVENT TIME-BASED HYSTERESIS (EHYS1, EHYS0) These bits set the amount of time-based hysteresis that is present at the EVIN pin for deglitching the input signal. The settings vary from 0ms (hysteresis OFF) to 31.25ms (delay of 31.25ms to check for change of state at the EVIN pin). The Hysteresis function and the Event Input Sampling function work independently.
TABLE 10. EVENT TIME-BASED HYSTERESIS EHSYS1 0 0 1 1 EHSYS0 0 1 0 1 TIME (ms) 0 3.9 16.625 31.25
1
Event Index Register (EVIX)
TABLE 12. EVENT INDEX REGISTER (EVIX) ADDR 0Fh 7 X 6 X 5 X 4 X 3 X 2 X 1 EVIX1 0 EVIX0
The Event Index Register provides the index for locating an individual event that has been stored. The Event recording function allows recalling up to 4 events, although the Event counting register will count up to 255 events. The 0th location corresponds to the first event, and the 1st through 3rd locations correspond to the most recent events, with the 3rd location (11b) representing the latest event. Therefore, setting EVIX to 03h location and reading the TSEVT section will access the timestamp information for the most recent (latest) event. Setting this register to another value will allow reading the corresponding event from the TSEVT section. EVENT BIT (EVIX <1:0>) These bits are the Event Counter Register index bits. EVIX1 is the MSB and EVIX0 is the LSB.
Trickle Charge Register (TRICK)
TABLE 13. TRICKLE CHARGE REGISTER (TRICK) ADDR 10h 7 X 6 X 5 X 4 X 3 X 2 1 0
TRKEN TRKRO1 TRKRO0
EVENT INPUT SAMPLING RATE (ESMP) These bits set the frequency of sampling of the Event Input (EVIN). The settings include from 1/4Hz (one sample per 4 seconds) to 2Hz (twice a second), 1Hz, or continuous sampling (Always ON). The less frequent the sampling, the lower the current drain, which can affect battery current drain and battery life.
The trickle charge function allows charging current to flow from the VDD supply to the VBAT pin through a selectable current limiting resistor. Diabling the trickle charge function removes this connection and isolates the battery from the VDD supply in the case charging is not necessary or harmful (as in the case with a lithium coin cell battery). Note that there is no charging diode in series with the trickle charge resistor, but a switch network that adds a small series resistance to the charging resistance. TRICKLE CHARGE BIT (TRKEN) This bit enables/disables the trickle charge capability for the backup battery supply. Setting this bit to "1" will enable the trickle charge. Resetting this bit to "0" will disable the trickle charge function and isolate the battery from the VDD supply. TRICKLE CHARGE RESISTOR (TRKRO<1:0>) These bits allow the user to change the trickle charge resistor settings according to the maximum current desired for the battery or supercapacitor charging.
16
FN6618.0 December 14, 2007
ISL12032
V DD - V BAT I MAX = -------------------------------R OUT TABLE 16. VDD TRIP LEVELS (EQ. 1) VDDTrip2 0 1 1 VDDTrip1 1 0 0 VDDTrip0 1 0 1 TRIP VOLTAGE (V) 3.060 4.250 4.675
Where the ROUT is the selected resistor between VDD and VBAT. Table 14 gives the typical resistor values for VDD = 5V and VBAT = 3.0V. Note that the resistor value changes with VDD input voltage and VBAT voltage, as well as with temperature..
TABLE 14. RESISTOR SELECTION REGISTER TRKRO1 0 0 1 1 TRKRO0 0 1 0 1 Rtrk 1300 2200 3600 7800 UNITS
Battery Voltage Warning Register (PWRVBAT)
This register controls the trip points for the two VBAT warnings, with levels set to approximately 85% and 75% of the nominal battery level.
TABLE 17. BATTERY VOLTAGE WARNING REGISTER (PWRVBAT) ADDR 7 6 5 4 3 2 1 0 12h X BHYS VB85T VB85T VB85T VB75T VB75T VB75T p2 p1 p0 p2 p1 p0
Power Supply Control Register (PWRVDD)
TABLE 15. POWER SUPPLY CONTROL REGISTER (PWRVDD) ADDR 11h 7 CLRTS 6 X 5 I2CBAT 4 LVENB 3 X 2 1 0
VBAT HYSTERESIS (BHYS) This bit enables/disables the hysteresis voltage for the VDD/VBAT switchover. When set to "1", hysteresis is enabled and switching to VBAT occurs at approximately 50mV below the VDD Trip point (set by VDDTrip<2:0>). Switching from VBAT to VDD power will occur at approximately 50mV above the VDD trip point. When set to "0", there is no hysteresis and switchover will occur at exactly the VDD trip point. Note that for slow moving VDD power-down and power-up signals there can be some extra switching cycles without hysteresis. BATTERY LEVEL MONITOR TRIP BITS (VB85TP <2:0>) Three bits selects the first alarm (85% of Nominal VBAT) level for the battery voltage monitor. There are total of 7 levels that could be selected for the first warning. Any of the levels could be selected as the first warning with no reference as to nominal VBAT voltage level. See Table 18 for typical values.
VDD VDD VDD Trip2 Trip1 Trip0
CLEAR TIME STAMP BIT (CLRTS) This bit clears both the Time Stamp VDD to Battery (TSV2B) and Time Stamp Battery to VDD (TSB2V) sections. The default setting is "0" which allows normal operation. Setting CLRTS = 1 performs the clear timestamp register function at the conclusion of a successful write operation. I2C IN BATTERY MODE (I2CBAT) This bit allows I2C operation in battery backup mode (VBAT powered) when set to "1". When reset to "0", the I2C operation is disabled in battery mode, which results in the lowest IDD current. Note that when the I2C operation is desired in VBAT mode, the SCL and SDA pull-ups must go to the VBAT source for proper communications. This will result in additional VBAT current drain (on top of the increased device VBAT current) during serial communications. VDD BROWNOUT TRIP VOLTAGE (VDDTRIP <2:0>) These bits set the 6 trip levels for the VDD alarm and VBAT switchover. The LVDD bit in the SRDC is set to "1" when VDD drops below this preset level. See Table 16.
TABLE 16. VDD TRIP LEVELS TRIP VOLTAGE (V) 2.295 2.550 2.805
VDDTrip2 0 0 0
VDDTrip1 0 0 1
VDDTrip0 0 1 0
17
FN6618.0 December 14, 2007
ISL12032
TABLE 18. VB85T VBAT WARNING LEVELS BATTERY ALARM TRIP LEVEL (V) 2.125 2.295 2.550 2.805 3.060 4.250 4.675 0 0 1 1
AC RECOVERY PERIOD (ACRP<1:0>) This bit sets the AC clock input validation recovery period. After the AC input fails validation (ACFAIL = 1), a predefined period is used to test the frequency and voltage of the AC clock input. The range is from 2s to 16s.
TABLE 21. AC RECOVERY PERIOD ACRP1 ACRP0 0 1 0 1 RECOVERY TIME 2s 4s 8s 16s
VB85Tp2 0 0 0 0 1 1 1
VB85Tp1 0 0 1 1 0 0 1
VB85Tp0 0 1 0 1 0 1 0
BATTERY LEVEL MONITOR TRIP BITS (VB75TP <2:0>) Three bits selects the second warning (75% of Nominal VBAT) level for the battery voltage monitor. There are total of 7 levels that could be selected for the second monitor. Any of the levels could be selected as the second alarm with no reference as to nominal VBAT voltage level. See Table 19 for typical values.
TABLE 19. VB75T VBAT WARNING LEVELS BATTERY ALARM TRIP LEVEL (V) 1.875 2.025 2.250 2.475 2.700 3.750 4.125
AC FAILURE CYCLES (ACFP<1:0>) These two bits determine how many AC cycles are used for the AC clock qualification, or to disable the AC clock qualification. The range is from 1 AC cycle to 12 AC cycles or disable, and is also dependent on the AC5060 bit setting (see Table 22). The qualification logic will count the number of crystal cycles in the chosen AC period, and if the count is outside the window set by ACFC bits then the ACFAIL signal is set to "1". For example, if 10 cycles are chosen for 50Hz input, then during those 10 cycles there would need to be exactly 6554 crystal cycles. That number is subtracted from the actual count during the 10 AC cycles and the absolute value is compared to the error value set by ACFC. If the error were 10 crystal cycles and ACFC were set to 11b, then the allowable error would be 20 crystal cycles and the ACFAIL would be "0", or qualification has passed. If the actual error count were 22 cycles then the ACFAIL would be set to "1", qualification has failed.
.
VB75Tp2 0 0 0 0 1 1 1
VB75Tp1 0 0 1 1 0 0 1
VB75Tp0 0 1 0 1 0 1 0
TABLE 22. AC FAILURE CYCLES CYCLE USED for COUNT AC5060 = 0 1 6 12 AC5060=1 1 5 10 ACFP1 0 0 1 1 ACFP0 0 1 0 1
AC Register (AC)
This register sets the performance screening for the AC input.
TABLE 20. AC REGISTER ADDR 13h 7 6 5 4 3 2 1 0 AC5060 ACENB ACRP1 ACRP0 ACFP1 ACFP0 ACFC1 ACFC0
(Disabled)
AC 50/60HZ INPUT SELECT (AC5060) This bit selects either 50Hz or 60Hz powerline AC clock input frequency. Setting this bit to "0" selects a 60Hz input (default). Setting this bit to "1" selects a 50Hz input. AC ENABLE (ACENB) This bit will enable/disable the AC clock input. Setting this bit to "0" will enable the AC clock input (default). Setting this bit to "1" will disable the AC clock input. When the AC input is disabled, the crystal oscillator becomes the sole source for RTC and FOUT clocking.
AC/CRYSTAL FREQUENCY FAILURE CRITERION (ACFC<1:0>) These two bits determine the number of crystal cycles used for the error budget for the AC qualification (see Table 24). Two of the choices are for a fixed ppm criterion of 1 or 2 crystal cycles in just one AC cycle (independent of the ACFP setting). The other choices are for 1 or 2 crystal cycles per AC cycle, but includes the total number of cycles set by the ACFP. Using the example given for the ACFP bits previously mentioned: AC5060 = 1 (50Hz) ACFC = 11b (2 xstal cycles/AC cycle)
18
FN6618.0 December 14, 2007
ISL12032
ACFP = 11b (10 total AC cycles) So the resulting crystal cycle count must be within: (10 AC cycles x 2 crystal cycles/AC cycle) or 20 total crystal cycles (error budget) as shown in Table 23.
TABLE 23. AC/CRYSTAL FREQUENCY FAILURE CRITERION TOTAL XTAL CYCLE ERROR BUDGET ACFP x 1 ACFP x 2 1 2 XDTR3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 XDTR2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 XDTR1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 XDTR0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 TABLE 25. XDTR FREQUENCY COMPENSATION FREQUENCY COMPENSATION (ppm) 0 10 20 30 40 50 60 0 0 -10 -20 -30 -40 -50 -60 0
ACFC1 0 0 1 1
ACFC0 0 1 0 1
CRITERION 1 crystal cycle per AC cycle 2 crystal cycle per AC cycle 1 crystal cycle in all AC cycles 2 crystal cycles in all AC cycles
Fine Trim Compensation Register (FTR)
This register (Table 24) provides control of the crystal oscillator clock compensation and the AC clock input minimum level detect.
TABLE 24. FINE TRM COMPENSATION REGISTER ADDR 14h 7 X 6 X 5 X 4 3 2 1 0 ACMIN XDTR3 XDTR2 XDTR1 XDTR0
DST Control Registers (DSTCR)
8 bytes of control registers have been assigned for the Daylight Savings Time (DST) functions. DST beginning (set Forward) time is controlled by the registers DstMoFd, DstDwFd, DstDtFd, and DstHrFd. DST ending time (set Backward or Reverse) is controlled by DstMoRv, DstDwRv, DstDtRv and DstHrRv. Tables 26 and 27 describe the structure and functions of the DSTCR. DST FORWARD REGISTERS (15H TO 18H) DSTE is the DST Enabling Bit located in bit 7 of register 15h (DstMoFdxx). Set DSTE = 1 will enable the DSTE function. Upon powering up for the first time (including battery), the DSTE bit defaults to "0". DST forward is controlled by the following DST Registers: DstMoFd sets the Month that DST starts. The default value for the DST begin month is April (04h). DstDwFd sets the Day of the Week that DST starts. DstDwFdE sets the priority of the Day of the Week over the Date. For DstDwFdE=1, Day of the week is the priority. Note that Day of the week counts from 0 to 6, like the RTC registers. The default for the DST Forward Day of the Week is Sunday (00h). DstDtfd controls which Date DST begins. The default value for DST forward date is on the first date of the month (01h). DstDtFd is only effective if DstDwFdE = 0.
AC MINIMUM (ACMIN) This bit determines the minimum peak-to-peak voltage level for the AC clock input as a percentage of the existing VDD supply. ACMIN = 0 sets the minimum level to 5% x VDD. ACMIN = 1 sets the minimum level to 10% x VDD. DIGITAL TRIM REGISTER (XDTR<3:0>) The digital trim register bits control the amount of trim used to adjust for the crystal clock error. This trim is accomplished by adding or subtracting the 32kHz clock in the clock counter chain to adjust the RTC clock. Calibration can be done by monitoring the FOUT pin with a frequency counter with the frequency output set to 1.0Hz, with no AC input.
19
FN6618.0 December 14, 2007
ISL12032
DstHrFd controls the hour that DST begins. It includes the MIL bit, which is in the corresponding RTC register. The RTC hour and DstHrFd registers need to match formats (Military or AM/PM) in order for the DST function to work. The default value for DST hour is 2:00AM (02h). The time is advanced from 2:00:00AM to 3:00:00AM for this setting. DST REVERSE REGISTERS (19H TO 1CH) DST end (reverse) is controlled by the following DST Registers. DstMoRv sets the Month that DST ends. The default value for the DST end month is October (10h). DstDwRv controls the Day of the Week that DST should end. The DwRvE bit sets the priority of the Day of the Week over
TABLE 26. DST FORWARD REGISTERS ADDRESS 15h 16h 17h 18h FUNCTION Month Forward Day Forward Date Forward Hour Forward 7 DSTE 0 0 HrFdMIL 6 0 DwFdE 0 0 5 0 WkFd12 DtFd21 HrFd21 4 MoFd20 WkFd11 DtFd20 HrFd20 3 MoFd13 WkFd10 DtFd13 HrFd13 2 MoFd12 DwFd12 DtFd12 HrFd12 1 MoFd11 DwFd11 DtFd11 HrFd11 0 MoFd10 DwFd10 DtFd10 HrFd10
the Date. For DwRvE = 1, Day of the week is the priority. Note that Day of the week counts from 0 to 6, like the RTC registers. The default for DST DwRv end is Sunday (00h). DstDtRv controls which Date DST ends. The default value for DST Date Reverse is on the first date of the month. The DstDtRv is only effective if the DwRvE = 0. DstHrRv controls the hour that DST ends. It includes the MIL bit, which is in the corresponding RTC register. The RTC hour and DstHrRv registers need to match formats (Military or AM/PM) in order for the DST function to work. The default value sets the DST end at 2:00AM. The time is set back from 2:00:00AM to 1:00:00AM for this setting.
TABLE 27. DST REVERSE REGISTERS ADDRESS 19h 1Ah 1Bh 1Ch NAME Month Reverse Day Reverse Date Reverse Hour Reverse 7 0 0 0 HrRvMIL 6 0 DwRvE 0 0 5 0 WkRv12 DtRv21 HrRv21 4 MoRv20 WkRv11 DtRv20 HrRv20 3 MoRv13 WkRv10 DtRv13 HrRv13 2 MoRv12 DwRv12 DtRv12 HrRv12 1 MoRv11 DwRv11 DtRv11 HrRv11 0 MoRv10 DwRv10 DtRv10 HrRv10
ALARM Registers (1Dh to 28h)
The alarm register bytes are set up identical to the RTC register bytes, except that the MSB of each byte functions as an enable bit (enable = "1"). These enable bits specify which alarm registers (seconds, minutes, etc.) are used to make the comparison. Note that there is no alarm byte for year. The alarm function works as a comparison between the alarm registers and the RTC registers. As the RTC advances, the alarm will be triggered once a match occurs between the alarm registers and the RTC registers. Any one alarm register, multiple registers, or all registers can be enabled for a match. There are two alarm operation modes: Single Event and periodic Interrupt Mode: Single Event Mode is enabled by setting either ALE0 or ALE1 to 1, then setting bit 7 on any of the Alarm registers (ESCA... EDWA) to "1", and setting the IM bit to "0". This mode permits a one-time match between the Alarm registers and the RTC registers. Once this match occurs, the ALM bit is set to "1" and the IRQ output will be pulled LOW and will remain LOW until the ALM bit is reset. This can be done 20
manually or by using the auto-reset feature. Since the IRQ output is shared by both alarms, they both need to be reset in order for the IRQ output to go HIGH. Interrupt Mode is enabled by setting either ALE0 or ALE1 to 1, then setting bit 7 on any of the Alarm registers (ESCA... EDWA) to "1", and setting the IM bit to "1". Setting the IM bit to 1 puts both ALM0 and ALM1 into Interrupt mode. The IRQ output will now be pulsed each time an alarm occurs (either AL0 or AL1). This means that once the interrupt mode alarm is set, it will continue to alarm until it is reset. To clear a single event alarm, the corresponding ALM0 or ALM1 bit in the SRDC register must be set to "0" with a write. Note that if the ARST bit is set to "1" (address 0Ch, bit 7), the ALM0 and ALM1 bits will automatically be cleared when the status register is read. The IRQ output will be set by an alarm match for either ALM0 or ALM1. Following are examples of both Single Event and periodic Interrupt Mode alarms.
FN6618.0 December 14, 2007
ISL12032
Example 1 * Alarm set with single interrupt (IM = "0") * A single alarm will occur on January 1 at 11:30am. * Set Alarm registers as follows:
ALARM REGISTER 7 SCA0 MNA0 HRA0 DTA0 MOA0 DWA0 0 1 1 1 1 0 BIT 6 0 0 0 0 0 0 5 0 1 0 0 0 0 4 0 1 1 0 0 0 3 0 0 0 0 0 0 2 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 1 0 HEX DESCRIPTION
Note that the status register ALM0 bit will be set each time the alarm is triggered, but does not need to be read or cleared.
Time Stamp VDD to Battery Registers (TSV2B)
The TSV2B section bytes are identical to the RTC register section, except they do not extend beyond the Month. The Time Stamp captures the FIRST VDD to Battery Voltage transition time, and will not update upon subsequent events, until cleared (only the first event is captured before clearing). Set CLRTS = 1 to clear this register (Addr 11h, PWRVDD register).
00h Seconds disabled B0h Minutes set to 30, enabled 91h Hours set to 11, enabled 81h Date set to 1, enabled 81h Month set to 1, enabled 00h Day of week disabled
Time Stamp Battery to VDD Registers (TSB2V)
The Time Stamp Battery to VDD section bytes are identical to the RTC section bytes, except they do not extend beyond Month. The Time Stamp captures the LAST transition of VBAT to VDD (only the last power up event of a series of power up/down events is retained). Set CLRTS = 1 to clear this register (Addr 11h, PWRVDD register).
Time Stamp Event Registers (TSEVT)
The TSEVT section bytes are identical to the RTC section bytes, except they do not extend beyond the Month. The Time Stamp captures the first event and the most recent three events. The first event Time Stamp will not update until cleared. All 4 Time Stamps are all cleared to "0" when writing the event counter (0Bh) is set to "0". Note: The time stamp registers are cleared to all "0", including the month and day, which is different from the RTC and alarm registers (those registers default to 01h). This is the indicator that no time stamping has occurred since the last clear or initial power-up. Once a time stamp occurs, there will be a non-zero time stamp.
After these registers are set, an alarm will be generated when the RTC advances to exactly 11:30 a.m. on January 1 (after seconds changes from 59 to 00) by setting the ALM0 bit in the status register to "1" and also bringing the IRQ output LOW. Example 2 * Pulsed interrupt once per minute (IM = "1") * Interrupts at one minute intervals when the seconds register is at 30 seconds. * Set Alarm registers as follows:
BIT ALARM REGISTER 7 6 5 4 3 2 1 0 HEX SCA0 MNA0 HRA0 DTA0 MOA0 DWA0
DESCRIPTION
1 0 1 1 0 0 0 0 B0h Seconds set to 30, enabled 0 0 0 0 0 0 0 0 00h Minutes disabled 0 0 0 0 0 0 0 0 00h Hours disabled 0 0 0 0 0 0 0 0 00h Date disabled 0 0 0 0 0 0 0 0 00h Month disabled 0 0 0 0 0 0 0 0 00h Day of week disabled
User Memory Registers (accessed by using Slave Address 1010111x)
Addresses [00h to 7Fh]
These registers are 128 bytes of battery-backed user SRAM. Writes to this section do not need to be proceeded by setting the WRTC bit.
I2C Serial Interface
The ISL12032 supports a bi-directional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is the master and the device being controlled is the slave. The master always initiates data transfers and provides the clock for both transmit and receive operations. Therefore, the ISL12032 operates as a slave device in all applications. All communication over the I2C interface is conducted by sending the MSB of each byte of data first.
Once the registers are set, the following waveform will be seen at IRQ:
RTC AND ALARM REGISTERS ARE BOTH "30s"
60s
FIGURE 5. IRQ WAVEFORM
21
FN6618.0 December 14, 2007
ISL12032
Protocol Conventions
Data states on the SDA line can change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions (see Figure 6). On power up of the ISL12032, the SDA pin is in the input mode. All I2C interface operations must begin with a START condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The ISL12032 continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition is met (see Figure 6). A START condition is ignored during the power-up sequence. All I2C interface operations must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is HIGH (see Figure 6). A STOP condition at the end of a read operation or at the end of a write operation to memory only places the device in its standby mode. An acknowledge (ACK) is a software convention used to indicate a successful data transfer. The transmitting device, either master or slave, releases the SDA bus after transmitting eight bits. During the ninth clock cycle, the receiver pulls the SDA line LOW to acknowledge the reception of the eight bits of data (See Figure 7). The ISL12032 responds with an ACK after recognition of a START condition followed by a valid Identification Byte, and once again after successful receipt of an Address Byte. The ISL12032 also responds with an ACK after receiving a Data Byte of a write operation. The master must respond with an ACK after receiving a Data Byte of a read operation.
SCL
SDA
START
DATA STABLE
DATA CHANGE
DATA STABLE
STOP
FIGURE 6. VALID DATA CHANGES, START AND STOP CONDITIONS
SCL FROM MASTER
1
8
9
SDA OUTPUT FROM TRANSMITTER
HIGH IMPEDANCE
SDA OUTPUT FROM RECEIVER
HIGH IMPEDANCE
START
ACK
FIGURE 7. ACKNOWLEDGE RESPONSE FROM RECEIVER
WRITE SIGNALS FROM THE MASTER S T A R T S T O P
IDENTIFICATION BYTE
ADDRESS BYTE
DATA BYTE
SIGNAL AT SDA SIGNALS FROM THE ISL12032
11011110 A C K
0000 A C K A C K
FIGURE 8. BYTE WRITE SEQUENCE (SLAVE ADDRESS FOR CSR SHOWN)
22
FN6618.0 December 14, 2007
ISL12032 Device Addressing
Following a start condition, the master must output a Slave Address Byte. The 7 MSBs are the device identifier. These bits are "1101111b" for the RTC registers and "1010111b" for the User SRAM. The last bit of the Slave Address Byte defines a read or write operation to be performed. When this R/W bit is a "1", then a read operation is selected. A "0" selects a write operation (refer to Figure 9). After loading the entire Slave Address Byte from the SDA bus, the ISL12032 compares the device identifier and device select bits with "1101111b" or "1010111b". Upon a correct compare, the device outputs an acknowledge on the SDA line. Following the Slave Byte is a one byte word address. The word address is either supplied by the master device or obtained from an internal counter. On power up the internal address counter is set to address 00h, so a current address read starts at address 00h. When required, as part of a random read, the master must supply the 1 Word Address Byte as shown in Figure 9. In a random read operation, the slave byte in the "dummy write" portion must match the slave byte in the "read" section. For a random read of the Control/Status Registers, the slave byte must be "1101111x" in both places.
1 1 0 1 1 1 1 R/W SLAVE ADDRESS BYTE
Write Operation
A Write operation requires a START condition, followed by a valid Identification Byte, a valid Address Byte, a Data Byte, and a STOP condition. After each of the three bytes, the ISL12032 responds with an ACK. At this time, the I2C interface enters a standby state. A multiple byte operation within a page is permitted. The Address Byte must have the start address, and the data bytes are sent in sequence after the address byte, with the ISL12032 sending an ACK after each byte. The page write is terminated with a STOP condition from the master. The pages within the ISL12032 do not support wrapping around for page read or write operations.
Read Operation
A Read operation consists of a three byte instruction followed by one or more Data Bytes (See Figure 10). The master initiates the operation issuing the following sequence: a START, the Identification byte with the RW bit set to "0", an Address Byte, a second START, and a second Identification byte with the RW bit set to "1". After each of the three bytes, the ISL12032 responds with an ACK. Then the ISL12032 transmits Data Bytes as long as the master responds with an ACK during the SCL cycle following the eighth bit of each byte. The master terminates the read operation (issuing a STOP condition) following the last bit of the last Data Byte (see Figure 10). The Data Bytes are from the memory location indicated by an internal pointer. This pointers initial value is determined by the Address Byte in the Read operation instruction, and increments by one during transmission of each Data Byte. After reaching the last memory location in a section or page, the master should issue a STOP. Bytes that are read at addresses higher than the last address in a section may be erroneous.
A7
A6
A5
A4
A3
A2
A1
A0
WORD ADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
DATA BYTE
FIGURE 9. SLAVE ADDRESS, WORD ADDRESS, AND DATA BYTES
SIGNALS FROM THE MASTER
S T A R T
IDENTIFICATION BYTE WITH R/W=0
ADDRESS BYTE
S T IDENTIFICATION A BYTE WITH R R/W = 1 T
A C K
A C K
S T O P
SIGNAL AT SDA SIGNALS FROM THE SLAVE
11011110 A C K A C K
11011111 A C K
FIRST READ DATA BYTE
LAST READ DATA BYTE
FIGURE 10. READ SEQUENCE (CSR SLAVE ADDRESS SHOWN)
23
FN6618.0 December 14, 2007
ISL12032 Application Section
Oscillator Crystal Requirements
The ISL12032 uses a standard 32.768kHz crystal. Either through hole or surface mount crystals can be used. Table 28 lists some recommended surface mount crystals and the parameters of each. This list is not exhaustive and other surface mount devices can be used with the ISL12032 if their specifications are very similar to the devices listed. The crystal should have a required parallel load capacitance of 12.5pF and an equivalent series resistance of less than 50k. The crystal's temperature range specification should match the application. Many crystals are rated for -10C to +60C (especially through hole and tuning fork types), so an appropriate crystal should be selected if extended temperature range is required.
TABLE 28. SUGGESTED SURFACE MOUNT CRYSTALS MANUFACTURER Citizen Epson Raltron SaRonix Ecliptek ECS Fox PART NUMBER CM200S MC-405, MC-406 RSM-200S 32S12 ECPSM29T-32.768K ECX-306 FSM-327
and VDD pins can be treated as a ground, and should be routed around the crystal.
AC Input Circuits
The AC input ideally will have a 2.5VP-P sine wave at the input, so this is the target for any signal conditioning circuitry for the 50/60Hz waveform. Note that the peak-to-peak amplitude can range from 1VP-P up to VDD, although it is best to keep the max signal level just below VDD. The AC input provides DC offset so AC coupling with a series capacitor is advised. If the AC power supply has a transformer, the secondary output can be used for clocking with a resistor divider and series AC coupling capacitor. A sample circuit is shown in Figure 12. Values for R1/R2 are chosen depending on the peak-to-peak range on the secondary voltage in order to match the input of the ISL12032. CIN can be sized to pass up to 300Hz or so, and in most cases, 0.47F should be the selected value for a 20% tolerance device. The AC input to the IS12032 can be damaged if subjected to a normal AC waveform when VDD is powered down. this can happen in circuits where there is a local LDO or power switch for placing circuitry in standby, while the AC main is still switched ON. Figure 11 shows a modified version of the Figure 12 circuit, which uses an emitter follower to essentially turn off the AC input waveform if the VDD supply goes down.
Using the ISL12032 with No AC Input Layout Considerations
The crystal input at X1 has a very high impedance, and oscillator circuits operating at low frequencies (such as 32.768kHz) are known to pick up noise very easily if layout precautions are not followed. Most instances of erratic clocking or large accuracy errors can be traced to the susceptibility of the oscillator circuit to interference from adjacent high speed clock or data lines. Careful layout of the RTC circuit will avoid noise pickup and ensure accurate clocking. Two main precautions for crystal PC board layout should be followed: 1. Do not run the serial bus lines or any high speed logic lines in the vicinity of the crystal. These logic level lines can induce noise in the oscillator circuit to cause misclocking. 2. Add a ground trace around the crystal with one end terminated at the chip ground. This will provide termination for emitted noise in the vicinity of the RTC device. In addition, it is a good idea to avoid a ground plane under the X1 and X2 pins and the crystal, as this will affect the load capacitance and therefore the oscillator accuracy of the circuit. If the FOUT pin is used as a clock, it should be routed away from the RTC device as well. The traces for the VBAT Some applications may need all the features of the ISL12032 but do not have access to the power line AC clock, or do not need the accuracy provided by that clock. In these cases there is no problem using the crystal oscillator as the primary clock source for the device. The user must simply set the ACENB bit in register 13h to "1", which disables the AC input pin and forces the device to use the crystal oscillator exclusively for the RTC and FOUT clock source. Setting this bit to "1" also will cause the ACRDY bit in the SRAC register to be set to "1", indicating that there can be no fault with the AC input clock since it is not used.
24
FN6618.0 December 14, 2007
ISL12032
VIN (AC) = 1.5VP-P to VDD (MAX) R1 CIN
120VAC 50/60Hz
R2
ISL12032
FIGURE 11. AC INPUT USING A TRANSFORMER SECONDARY
VIN (AC) = 1.5VP-P to VDD (MAX) VDD
R1
C1 CIN
120VAC 50/60Hz
R2
ISL12032
FIGURE 12. USING THE VDD SUPPLY TO GATE THE AC INPUT
.
25
FN6618.0 December 14, 2007
ISL12032 Thin Shrink Small Outline Plastic Packages (TSSOP)
N INDEX AREA E E1 -B1 2 3 0.05(0.002) -AD -CSEATING PLANE A 0.25 0.010 L 0.25(0.010) M GAUGE PLANE BM
M14.173
14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 b c MIN 0.002 0.031 0.0075 0.0035 0.195 0.169 0.246 0.0177 14 0o 8o 0o MAX 0.047 0.006 0.041 0.0118 0.0079 0.199 0.177 0.256 0.0295 MILLIMETERS MIN 0.05 0.80 0.19 0.09 4.95 4.30 6.25 0.45 14 8o MAX 1.20 0.15 1.05 0.30 0.20 5.05 4.50 6.50 0.75 NOTES 9 3 4 6 7 Rev. 2 4/06
e
b 0.10(0.004) M C AM BS
A1 0.10(0.004)
A2 c
D E1 e E L N
0.026 BSC
0.65 BSC
NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 26
FN6618.0 December 14, 2007

▲Up To Search▲

Price & Availability of ISL12032IVZ

	To Download ISL12032IVZ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .